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| Philips Semiconductors Product specification PowerMOS transistor Logic level FET GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor in a plastic envelope suitable for surface mount applications. The device is intended for use in automotive and general purpose switching applications. BUK565-60H QUICK REFERENCE DATA SYMBOL VDS ID Ptot Tj RDS(ON) PARAMETER Drain-source voltage Drain current (DC) Total power dissipation Junction temperature Drain-source on-state resistance; VGS = 5 V MAX. 60 41 125 175 38 UNIT V A W C m PINNING - SOT404 PIN 1 2 3 mb gate drain DESCRIPTION PIN CONFIGURATION mb SYMBOL d g source drain 1 2 3 s LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS VGSM ID ID IDM Ptot Tstg Tj PARAMETER Drain-source voltage Drain-gate voltage Gate-source voltage Non-repetitive gate-source voltage Drain current (DC) Drain current (DC) Drain current (pulse peak value) Total power dissipation Storage temperature Junction temperature CONDITIONS RGS = 20 k tp 50 s Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 60 60 15 20 41 29 164 125 175 175 UNIT V V V V A A A W C C THERMAL RESISTANCES SYMBOL Rth j-mb Rth j-a PARAMETER Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. minimum footprint, FR4 board (see Fig. 18) 50 MAX. 1.2 UNIT K/W K/W June 1995 1 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET STATIC CHARACTERISTICS Tmb = 25 C unless otherwise specified SYMBOL V(BR)DSS VGS(TO) IDSS IDSS IGSS RDS(ON) PARAMETER Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current Zero gate voltage drain current Gate source leakage current Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 0.25 mA VDS = VGS; ID = 1 mA VDS = 60 V; VGS = 0 V; Tj = 25 C VDS = 60 V; VGS = 0 V; Tj =125 C VGS = 15 V; VDS = 0 V VGS = 5 V; ID = 20 A MIN. 60 1.0 - BUK565-60H TYP. 1.5 1 0.1 10 25 MAX. 2.0 10 1.0 100 38 UNIT V V A mA nA m DYNAMIC CHARACTERISTICS Tmb = 25 C unless otherwise specified SYMBOL gfs Ciss Coss Crss td on tr td off tf Ld Ld Ls PARAMETER Forward transconductance Input capacitance Output capacitance Feedback capacitance Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance CONDITIONS VDS = 25 V; ID = 20 A VGS = 0 V; VDS = 25 V; f = 1 MHz MIN. 11 TYP. 20 1200 470 180 25 120 160 110 3.5 4.5 7.5 MAX. 1750 600 275 40 150 220 145 UNIT S pF pF pF ns ns ns ns nH nH nH VDD = 30 V; ID = 3 A; VGS = 5 V; RGS = 50 ; Rgen = 50 Measured from contact screw on tab to centre of die Measured from drain lead 6 mm from package to centre of die Measured from source lead 6 mm from package to source bond pad REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS Tmb = 25 C unless otherwise specified SYMBOL IDR IDRM VSD trr Qrr PARAMETER Continuous reverse drain current Pulsed reverse drain current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS IF = 41 A ; VGS = 0 V IF = 41 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V MIN. TYP. 0.95 60 0.30 MAX. 41 164 2.0 UNIT A A V ns C AVALANCHE LIMITING VALUE Tmb = 25 C unless otherwise specified SYMBOL WDSS PARAMETER Drain-source non-repetitive unclamped inductive turn-off energy CONDITIONS ID = 41 A ; VDD 25 V ; VGS = 5 V ; RGS = 50 MIN. TYP. MAX. 90 UNIT mJ June 1995 2 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H 120 110 100 90 80 70 60 50 40 30 20 10 0 PD% Normalised Power Derating 10 Zth j-mb / (K/W) BUKx55-lv 1 D= 0.5 0.2 0.1 0.05 0.02 0 P D tp D= tp T t 1E+01 0.1 0.01 0 20 40 60 80 100 Tmb / C 120 140 160 180 0.001 1E-07 T 1E-05 1E-03 t/s 1E-01 Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb) ID% Normalised Current Derating Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T ID / A 15 80 10 6 5 4.5 60 4 40 3.5 3 VGS / V = 2.5 BUK5Y5-60H 120 110 100 90 80 70 60 50 40 30 20 10 0 100 20 0 20 40 60 80 100 Tmb / C 120 140 160 180 0 0 2 4 VDS / V 6 8 10 Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb); conditions: VGS 5 V Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS 1000 ID / A BUK555-60H 0.2 RDS(ON) / Ohm 2.5 3 3.5 4 4.5 BUK5Y5-60H 100 RD O S( N) = VD S/ ID tp = 10 us 100 us 0.15 VGS / V = 5 0.1 10 0.05 6 15 10 DC 1 ms 10 ms 100 ms 1 1 10 VDS / V 100 0 0 20 40 ID / A 60 80 100 Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID); parameter VGS June 1995 3 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H 100 ID / A BUK5Y5-60H VGS(TO) / V max. 80 2 typ. 60 1 min. 40 20 Tj / C = -40 25 150 0 0 1 2 3 4 VGS / V 5 6 7 8 0 -60 -20 20 60 Tj / C 100 140 180 Fig.7. Typical transfer characteristics. ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj gfs / S BUK5Y5-60H Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS ID / A SUB-THRESHOLD CONDUCTION 40 1E-01 1E-02 30 1E-03 2% typ 98 % 20 1E-04 10 Tj / C = -40 25 150 1E-05 0 1E-06 0 20 40 ID / A 60 80 100 0 0.4 0.8 1.2 VGS / V 1.6 2 2.4 Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID); conditions: VDS = 10 V a Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS C / pF 2.0 Normalised RDS(ON) = f(Tj) 10000 BUK5Y5-60H Ciss Coss Crss 1.5 1.0 1000 0.5 0 -60 -20 20 60 Tj / C 100 140 180 100 0.1 1 VDS / V 10 100 Fig.9. Normalised drain-source on-state resistance. a = RDS(ON)/RDS(ON)25 C = f(Tj); ID = 20 A; VGS = 5 V Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz June 1995 4 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET BUK565-60H 15 VGS / V BUK5Y5-60H 120 110 100 WDSS% VDD / V = 12 10 48 90 80 70 60 50 5 40 30 20 10 0 0 10 20 30 40 QG / nC 50 60 70 80 0 20 40 60 80 100 120 Tmb / C 140 160 180 Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); conditions: ID = 41 A; parameter VDS IS / A 100 Tj / C = -40 25 150 Fig.15. Normalised avalanche energy rating. WDSS% = f(Tmb); conditions: ID = 41 A BUKXY5-60H + L VDS VDD 80 60 VGS 40 -ID/100 T.U.T. R 01 shunt 0 20 RGS 0 0 0.5 VSDS / V 1 1.5 Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj Fig.16. Avalanche energy test circuit. 2 WDSS = 0.5 LID BVDSS /(BVDSS - VDD ) June 1995 5 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET MECHANICAL DATA Dimensions in mm Net Mass: 1.4 g 10.3 max 4.5 max 1.4 max BUK565-60H 11 max 15.4 2.5 0.85 max (x2) 2.54 (x2) 0.5 Fig.17. SOT404 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 11.5 9.0 17.5 2.0 3.8 5.08 Fig.18. SOT404 : soldering pattern for surface mounting. Notes 1. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide. 2. Epoxy meets UL94 V0 at 1/8". June 1995 6 Rev 1.000 Philips Semiconductors Product specification PowerMOS transistor Logic level FET DEFINITIONS Data sheet status Objective specification Product specification Limiting values BUK565-60H This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. June 1995 7 Rev 1.000 Error Log 565-60.H 1) Level: Format Error Message: Word is wider than column Location: Document Body Page: 1 Distance from TOF: 7.14cm Level: 1 Section: 1 Block: Text #1 Column: 6 level field-effect power transistor in Page E1 96-11-11 04:15 pm |
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